1. Field of the Invention
The present invention relates to a data transfer apparatus including communication ports for communicating packet data, relates to a data transfer device, and relates to a data transfer method for a data transfer apparatus.
2. Description of the Related Art
The high-speed serial transmission technology using such as the peripheral component interconnect (PCI) express (hereinafter, referred to as “PCIe”) technology has become popular and is also being implemented for image buses installed in multifunction peripherals or the like. In recent years, along with the popularization of the PCIe technology, there has been a rise in demands for expanding the implementation of the high-speed serial transmission technology into inter-device communication via cables, not confining the use only to the inside of devices. Consider the implementation of the high-speed serial transmission technology into multifunction peripherals. For example, if the controller and the printing apparatus in a large-scale printer that is used in the printing industry are disposed apart from each other; then it is conceivable to connect the image data bus by a cable.
One characteristic of the high-speed serial transmission technology is splitting data into packets for transmission. As compared to the typical parallel data transmission technology, the serial data transmission technology is operated on a wider data transfer bandwidth but at the same time has an increased delay time required for transfer. Hence, in the case of long-distance transmission using a cable, if a device having no consideration given to cable connection is connected as it is; then the increased delay time due to the cable connection causes a delay in receiving acknowledgment (ACK) packets as the response from addressee devices. That leads to the occurrence of timeouts thereby causing to decline in the data transfer rate.
Explained below is the basic operational concept of the PCIe technology. FIG. 18 is a schematic diagram of an exemplary internal configuration of a common master device and a common target device employed in the PCIe technology. Firstly, consider a case when a PCIe circuit 50 functions as a master device. In that case, regarding a request (a memory write request or a memory read request, REQ) issued by a user circuit 52 to the PCIe circuit 50; the request reaches a TLP conversion unit 502 via a transmission port (TX) 501 and gets converted into a packet called a transaction layer packet (TLP) by the TLP conversion unit 502 so as to be stored in a transmission buffer 503.
Subsequently, a transmission flow control unit 504 determines whether a free space is available in the reception buffer of the addressee device. If a free space is available in the reception buffer of the addressee device, then a transmission port (TX) 505 transmits the TLP that has been stored in the transmission buffer 503.
The free space in the reception buffer of the addressee device is managed on the basis of credit information that is reported by the addressee device in a flow control (FC) packet. A reception port (RX) 511 receives the FC packet from the addressee device. Then, a credit detecting unit 513 detects a credit value from the FC packet and reports the credit value to the transmission flow control unit 504.
In order to enable TLP retransmission if the TLP that is transmitted via the transmission flow control unit 504 gets destroyed due to an error, a copy of the contents of the transmitted TLP is temporarily stored in a retransmission buffer 507. The addressee device responds with an ACK packet or a negative acknowledgement (NAK) packet as a notification about whether the TLP was received in the normal condition or not. Herein, the ACK packet indicates that the TLP was normally transmitted to the addressee device, while the NAK packet indicates that the TLP was not normally transmitted to the addressee device. An ACK/NAK detecting unit 514 detects whether the received packet is an ACK packet or an NAK packet, and reports the information regarding the same to a retransmission buffer control unit 506.
If an ACK packet is reported to have been received, then the retransmission buffer control unit 506 revokes the contents of the TLP stored in the retransmission buffer 507 under the assumption that the transmitted TLP has reached the addressee device in the normal condition. On the other hand, if an NAK packet is reported to have been received, then the retransmission buffer control unit 506 retransmits the TLP stored in the retransmission buffer 507 under the assumption that the transmitted TLP did not reach the addressee device in the normal condition.
Consider a case when the PCIe circuit 50 functions as a target device. When a TLP transmitted by a source device reaches the reception port (RX) 511, an error detecting unit 512 detects errors in the TLP on the basis of a cyclic redundancy check (CRC) value. If no error is detected, then the error detecting unit 512 transmits an ACK packet to the transmission port 505. On the other hand, if an error is detected, then the error detecting unit 512 transmits an NAK packet to the transmission port (TX) 505 and revokes the received TLP. When no error is detected, the received TLP is stored in a reception buffer 515. Besides, a TLP conversion unit 516 converts the received TLP into a request (REQ) that is compatible to the user circuit 52 and then transfers that request to the user circuit 52 via a reception port (RX) 517.
The transfer of the request to the user circuit 52 leads to the creation of a free space in the reception buffer 515. Then, a reception flow control unit 518 transmits, to the transmission port 505, an FC packet including the size of that free space as the credit information.
Meanwhile, generally, packets used to hold requests or data are referred to as TLPs; while packets such as ACK packets, NAK packets, and FC packets used for the control purpose are referred to as data link layer packets (DLLPs).
In this way, in the high-speed serial technology implemented for the packet transfer by a PCIe device; using a reception buffer, a transmission buffer, and a retransmission buffer enables achieving efficient data transfer as well as enables ensuring transmission of the data by allowing retransmission in case of errors. Each buffer is designed to have the optimum size with respect to the delay time taken for packet transfer with the addressee device or with respect to the processing capacity of each device. In a device having no consideration given to cable connection, the short delay time leads to a decrease in the installation cost. Thus, the configuration does not include large-sized buffers. Meanwhile, in the example illustrated in FIG. 18, each buffer is designed to store four packets.
FIG. 19A is a schematic diagram of an example when a master device 60 and a target device 70 are directly connected to each other. FIG. 19B is a schematic diagram of buffer configurations of the master device 60 and the target device 70. Herein, a transmission buffer 61 and a retransmission buffer 62 in the master device 60 and a reception buffer 71 in the target device 70 are 4-step buffers. Thus, a maximum of four TLPs can be issued before an ACK packet or an FC packet is received in response. When the master device 60 is directly connected to the target device 70 as illustrated in FIG. 19A, the response delay is short as illustrated by arrows in FIG. 19C and the reception of the first ACK packet/FC packet starts before completing the transmission of four TLPs. That makes it possible to keep transmitting the TLPs in an efficient manner without having to wait for the creation of a free space.
In contrast, as illustrated in FIGS. 20A and 20B, if the master device 60 and the target device 70 are connected by a cable, then there occurs an increase in the transmission path delay caused due to the cable length. In the exemplary timing diagram illustrated in FIG. 20C, the first ACK packet/FC packet is not received in response even after completing the transmission of four TLPs. Hence, the period up to the point of time when the subsequent four TLPs can be transmitted happens to be the transfer downtime. In this way, as compared to the case when the master device 60 and the target device are directly connected to each other, the data transfer efficiency decreases when the master device 60 and the target device are connected by a cable. From the exemplary timing diagram illustrated in FIG. 20C, it can be anticipated that about 6-step buffers to 8-step buffers are required to absorb the response delay.
FIG. 21 is a graph of an example of the relation between the transmission buffer size and the data transfer rate of the master device and the target device when a PCIe device is extended with a PCIe cable. FIG. 22 is a graph of an example of the relation between the cable length and the data transfer rate when a PCIe device is extended with a PCIe cable. In FIGS. 21 and 22, the vertical axis represents the data transfer rate at the time when memory read requests of 128 bytes per request are continuously issued by a PCIe x4 lane connection.
From the graph illustrated in FIG. 21, it can be understood that the data transfer rate starts to decrease when the transmission buffer size of the master device becomes equal to or less than 10. That happens because of a response wait time that is created when, after issuing the read requests equivalent to the transmission buffer size, the master device stops issuing subsequent requests until an ACK packet or an FC packet is received in response from the target device. In the graph illustrated in FIG. 22, the data transfer rate is given for a case when the transmission buffer size is fixed to eight, at which the data transfer rate decreases in the graph illustrated in FIG. 21, but when the cable length is varied. From the graph illustrated in FIG. 22, it can be understood that longer the cable length, larger is the decrease in the data transfer rate. In a condition when the data transfer rate decreases due to insufficient transmission buffer size, the time taken by the number of packets increased as a result of an increase in the cable length to pass through the cable is added as it is to the response wait time. For that reason, longer the cable length, longer is the response wait time and larger is the decrease in the data transfer efficiency. Meanwhile, in a condition when the transmission buffer size is sufficiently large against the response delay occurring due to the cable length, the increase in the time taken for cable propagation is not added to the response wait time. Hence, the data transfer rate does not decrease corresponding to the cable length as illustrated in the graph in FIG. 22.
With the purpose of achieving a high data transfer rate in the case of cable connection; a technology is disclosed for absorbing the transmission path delay by reconfiguring the master device, which functions as the transmission source, and the target device, which functions as the transmission destination, to include large buffers. Meanwhile, in the universal serial bus (USB) technology, in order to prevent timeouts occurring due to the cable extension while waiting for an ACK packet, a connection adaptor has been disclosed for the purpose of inserting a temporary buffer in the transmission path prior to the entry in the cable (e.g., see Japanese Patent Application Laid-open No. 2000-332791). Regarding the PCIe technology, a technology has been disclosed for nullifying the effect of the delay time by inserting a PCIe switch device including large-sized internal buffers.
FIG. 23 is a schematic diagram of an example of the conventional technology according to which a PCIe switch 80 is inserted in the transmission path between the master device 60 and the target device 70. FIG. 24 is a schematic diagram of an exemplary internal configuration of the common PCIe switch 80 in the conventional technology. From among three ports, namely, a first port 810, a second port 820, and a third port 830 illustrated in FIG. 24; the PCIe switch 80 makes use of two ports (the first port 810 and the second port 820) for the cable relay between the master device and the target device.
In the first port 810 on the side of the master device and in the second port 820 on the side of the target device, the PCIe circuit explained with reference to FIG. 18 is designed. The first port 810 and the second port 820 are connected via a port arbitration circuit 840. The first port 810 includes a reception buffer 811, a transmission buffer 812, and a retransmission buffer 813; while the second port 820 includes a reception buffer 821, a transmission buffer 822, and a retransmission buffer 823. Each of those buffers is an eight-step buffer. Herein, by inserting a switch device including large-sized buffers in the transmission path, there are times when it is possible to absorb the increase in the response delay occurring in the cable.
However, in a conventional apparatus performing the high-speed serial transmission using a cable, the abovementioned measure is nothing more than inserting a temporary buffer in the device or on the transmission path. The manufacturing of a device with a changed buffer size is an expensive task. Moreover, if the addressee device to be connected includes only small buffers, then the increased buffer size produces no effect. Besides, every time the length of the connected cable changes, it becomes necessary to change the buffer size, which involves some efforts.
In the serial transmission technology such as the PCIe technology in which it is allowed to transmit a plurality of packets without waiting for an ACK response, the data transfer efficiency cannot be enhanced just by shortening the ACK response time with the use of a connection adaptor for inserting a temporary buffer in the transmission path. In the technology of inserting a PCIe switch device that includes large-sized internal buffers, if balance is not maintained between the delay time occurring at the data transmission source device, the delay time occurring in the transmission path of the data transmission addressee device, and the sizes of the buffers on the transmission side and the reception side of the switch device; then the data transfer efficiency decreases. Besides, as the cable becomes longer, the data transfer rate decreases even if a free space is available in the internal buffers.